The present invention generally relates to equipment for testing semiconductor devices, and more specifically, to a dye and pry process for removing quad flat no-lead (QFN) packages and bottom termination components (BTC) from card assemblies.
Most integrated circuit components that are attached to a printed circuit board (PCB) are attached using mechanical means, such as soldering. In the past, when devices were relatively simple and included only a few leads going from each component to the board, a visual inspection could be made to determine whether the component-to-board bonding had been adequate and whether a good mechanical connection had been obtained with proper solder flow. Conventional surface mount technologies (SMT), however, are far more complicated and densely packed than legacy packages. For example, Land Grid Array (LGA) wiring/pad designs for silicon chip interconnection and Ball Grid Array (BGA) and Column Grid Array (CGA) type modules for silicon chip attachment or first level package attachment to a second level board electronic packaging assembly offer increased wire density over older peripheral component attachment schemes. Unfortunately, solder joints that are made on these more complicated packages cannot be visually inspected beneath the chip or component bodies after carrier attachment.
Instead, conventional packages are typically assessed using a destructive dye and pry technique. The “dye and pry” technique relies on a liquid dye that penetrates into existing micro cracks or under open solder balls to reveal defects on the solder ball to pad interface. This technique is a destructive test that requires the tested package to be submerged in dye and then baked at a relatively high temperature until the dye has set.